1. Field of the Invention
The present invention relates to a ferroelectric memory that uses a ferroelectric capacitor and a transistor to configure a memory cell.
2. Description of the Related Art
Storage devices using a ferroelectric capacitor as a storage medium, (ferroelectric memories), have been developed and practically used (see JP 2001-250376A). The ferroelectric memory is non-volatile and thus causes no loss of the stored content even after power-off. In addition, if it has a sufficiently thin film thickness, the inversion speed of spontaneous polarization is higher and enables fast write/read accordingly. These excellent characteristics are present in the ferroelectric memory. The ferroelectric memory is suitable for achievement of mass storage because one-bit memory cell can be composed of one transistor and one ferroelectric capacitor.
In recent years, among the ferroelectric memories, attention has been focused on a ferroelectric memory of the TC-parallel, unit-serial connection type. The ferroelectric memory of the TC parallel unit serial connection type includes a ferroelectric capacitor having a bottom electrode and a top electrode connected between a source and a drain of a cell transistor. The cell transistor and the ferroelectric capacitor form a unit cell (memory cell) and such unit cells are serially connected.
On information read from a specific memory cell (selected memory cell), the ferroelectric memory of the TC parallel unit serial connection type applies a potential to the capacitor in the selected memory cell via cell transistors in non-selected memory cells serially connected. The voltage on the capacitor in the selected memory cell is transferred to a bit line to read the state of storage in the memory cell.
For example, referring to a memory cell train located between BL and PL in FIG. 9 of Patent Document 1, memory cells, each including a ferroelectric capacitor and a cell transistor connected in parallel therewith, are serially connected. When a memory cell M0 is selected, the potential on the plate line PL to be applied to the ferroelectric capacitor in the selected cell or memory cell M0 is transferred through cell transistors in non-selected cells or memory cells MC1-MC7. In a word, the rise of the voltage difference across the both ends of the memory cell M0 is susceptible to the resistance of the cell transistors in the non-selected cells.
Thus, a difference in resistance of the cell transistors causes a difference in time required for the voltage difference across the both ends of the selected cell or memory cell to reach a certain level. A conventional FeRAM may cause a malfunction because a sense operation starts before the voltage difference reaches a certain level due to the difference in resistance of the cell transistors.
The cell transistors have respective shapes disturbed on production and uneven resistances. In a word, the time required for a cell node in the selected memory cell to reach a certain level can not be made constant. Therefore, the configuration of the cell transistors as above may cause a malfunction because a sense operation is executed before the cell node reaches a certain level. The unevenness among the resistances of the cell transistors causes a lowered yield in production of the ferroelectric memory of the TC parallel unit serial connection type.